Field of the Disclosure
The present disclosure relates to a built-in gate driver applied to a flat panel display device, and more particularly, to a built-in gate driver, which is provided in a panel configuring a flat panel display device.
Related Art
Flat Panel Display (FPD) devices are used in various electronic products such as portable phones, tablet PCs, notebooks, etc. The FPD devices include Liquid crystal Display (LCD) device, Plasma Display panels (PDPs), and Organic Light Emitting Display (OLED) Device, etc. Recently, Electrophoretic display (EPD) devices are being widely used as the FPD devices.
A FPD device includes a gate driver that sequentially supplies a pull-up signal to a plurality of gate lines.
The gate driver is configured as an integrated circuit (IC), and mounted on a panel of the FPD device. Recently, a gate-in panel (GIP) type gate driver in which a thin film transistor (TFT) and various elements configuring the gate driver are provided in the panel is widely used. Hereinafter, the GIP type gate driver is simply referred to as a built-in gate driver.
FIG. 1 is an exemplary diagram illustrating a configuration of a related art integrated gate driver, and FIG. 2 is an exemplary diagram illustrating an arrangement structure of lines applied to the related art integrated gate driver.
The related art integrated gate driver, as illustrated in FIG. 1, includes a shift register S that sequentially outputs a pull-up signal to a plurality of gate lines, a clock supply line part CLP for supplying various clocks to the shift register S, and a power supply line part PLP for supplying various powers to the shift register S.
The clock supply line part CLP includes at least two or more clock supply lines, and clocks having different periods or pulse widths are transferred through the clock supply lines.
The power supply line part PLP includes at least two or more power supply lines, and powers having the same voltage or different voltages are supplied through the power supply lines.
The shift register S includes a plurality of stages ST1 to STg including a plurality of transistors. The stages ST1 to STg are dependently connected to each other, and respectively output scan signals SS1 to SSg to the gate lines.
Each of the stages ST1 to STg applied to the shift register S configuring the built-in gate driver includes a pull-up transistor PU, which outputs the pull-up signal for turning on a switching transistor formed in each pixel of the panel, and a pull-down transistor PD that outputs a pull-down signal for turning off the switching transistor.
Each of the scan signals SS1 to SSg includes the pull-up signal for turning on the switching transistor and a pull-down signal for turning off the switching transistor.
The pull-up signal is output during one horizontal period, in which a data voltage is applied to the panel, in a partial section of one vertical period, and the pull-down signal is transferred to the gate line in the other section of the one vertical period.
In the related art integrated gate driver, as illustrated in FIG. 1, the clock supply lines configuring the clock supply line part CLP and the power supply lines configuring the power supply line part PLP are formed at one side of the shift register S. Hereinafter, for convenience of description, as illustrated in FIGS. 1 and 2, a case in which the built-in gate driver includes four clock supply lines CL1 to CL4 and n number of power supply lines PL1 to PLn will be described as an example of the related art integrated gate driver. In this case, first to fourth clocks CLK1 to CLK4 are respectively supplied through first to fourth clock supply lines CL1 to CL4, and first power to nth power Power1 to Power4 are respectively supplied through first to nth power supply lines PL1 to PLn.
Moreover, generally, the clock supply lines, the power supply lines, and the stages ST1 to STg long extend in an up and down direction of the panel.
In this case, delay of the pull-up signal output from the stages disposed at a lower end of the panel progressively increases in a direction from a g-3rd stage ST(g-3) to a gth stage STg.
The delay is caused by resistances of the clock supply lines and power supply lines themselves, or as illustrated in FIG. 2, the delay is caused by a parasitic capacitance which is generated at each of positions in which the clock supply lines CL1 to CL4 overlap the power supply lines PL1 to PLn.
For example, the first clock supply line CL1 of FIG. 2 overlaps the second to fourth clock supply lines CL2 to CIA and the first to nth power supply lines PL1 to PLn while a clock is being transferred to the shift register S. In this case, a parasitic capacitance is generated in an overlapping area, and the first clock CLK1 is delayed by the parasitic capacitance while the first clock CLK1 is being transferred to the stage. Due to the delay, the pull-up signal generated from the first clock is also delayed.
For the same reasons, the second to fourth clocks CLK2 to CLK4 are delayed, and due to the delay, pull-up signals respectively generated from the second to fourth clocks CLK2 to CLK4 are also delayed.
Delays of the pull-up signals, as described above, are caused by an overlap between the clock supply lines CL1 to CL4 and an overlap between the clock supply lines and the power supply lines, or are caused by a parasitic capacitance in the pull-up transistor included in each of the stages.
For example, a pull-up transistor for outputting the pull-up signal is formed in each of the stages, and a corresponding clock supply line or power supply line is connected to the pull-up transistor. That is, one of the clock supply lines is connected to a drain of the pull-up transistor, the gate line is connected to a source of the pull-up transistor, and a Q node of the stage is connected to a gate of the pull-up transistor.
In this case, a gate-drain parasitic capacitor Cgd is formed between the clock supply line and the Q node, and a gate-source parasitic capacitor Cgs is formed between the gate line and the Q node.
Delay of the pull-up signal is produced by the gate-drain parasitic capacitor Cgd.
In particular, when the shift register is configured with a coplanar-type transistor, an overlap of the clock line greatly affects the delay of the pull-up signal because the gate-drain parasitic capacitor Cgd is smaller than a different-type transistor.